DocumentCode :
2054193
Title :
Multiclock Esterel: a reactive framework for asynchronous design
Author :
Rajan, Basant ; Shyamasundar, R.K.
Author_Institution :
Fac. of Technol. & Comput. Sci., Tata Inst. of Fundamental Res., Bombay, India
fYear :
2000
fDate :
2000
Firstpage :
201
Lastpage :
209
Abstract :
In this paper, we discuss a new paradigm called Multiclock Esterel, based on the paradigm of the synchronous reactive language, Esterel, used for reactive systems and synchronous circuit design. We show that the Multiclock Esterel paradigm provides a general framework for the design of systems with multiple local clocks and the earlier paradigm of CRP (Communicating Reactive Processes) can be obtained as an instance of the newly proposed paradigm. Furthermore, it preserves the advantages of the classical Esterel paradigm and thus benefits from the advantages of verifiability of specifications/models. Multiclock Esterel provides a formal basis for designing asynchronous circuits and provides a succinct unification of synchrony and asynchrony
Keywords :
asynchronous circuits; logic design; specification languages; Multiclock Esterel; asynchronous design; asynchrony; classical Esterel paradigm; formal basis; multiple local clocks; reactive framework; reactive systems; specifications; succinct unification; synchronous circuit design; synchronous reactive language; synchrony; verifiability; Asynchronous circuits; Central Processing Unit; Circuit synthesis; Clocks; Computer science; Design automation; Energy consumption; Frequency; Hardware design languages; Synchronization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel and Distributed Processing Symposium, 2000. IPDPS 2000. Proceedings. 14th International
Conference_Location :
Cancun
Print_ISBN :
0-7695-0574-0
Type :
conf
DOI :
10.1109/IPDPS.2000.845982
Filename :
845982
Link To Document :
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