Low-power clock and data recovery circuit for IR-UWB receiver power management

A low power clock and data recovery (CDR) for low data rate applications is presented. The CDR circuit, implemented as a phase locked-loop (PLL), deals with very narrow pulses from an energy detector in a non-coherent Impulse Radio based Ultra Wide Band (IR-UWB) receiver. To considerably reduce the power consumption of such a receiver, the proposed circuit is intended to be used to turn off analog/RF blocks between detected pulses. For that, a modified Hogge-type phase detector (PD) is proposed that enables the PLL to efficiently work with “return-to-zero (RZ) low duty cycle” (UWB pulses) input data. A simple pre-charge circuit is added to reduce the PLL lock time. The circuit has been realized in a 0.13 μm CMOS technology. Process variations taken into account through corner simulations show that the loop locks for all corners. Post-layout simulations at typical corner parameters show a power consumption of only 16 μW, a lock time of 130 μs and a recovered clock peak-to-peak jitter of 25 ns (2.5% UI) for an input data rate of 1 Mb/s.