Title :
Reduction of micro-scratch using slurry filter in oxide CMP (chemical mechanical polishing) for multi-level interconnections
Author :
Kim, Chul-Bok ; Kim, Sang-Yong ; Seo, Yong-Jin
Author_Institution :
Dept. of Electr. Eng., Daebul Univ., Chonnam, South Korea
Abstract :
Chemical mechanical polishing (CMP) process has been widely used to planarize dielectrics, which can apply to integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of free-defects in the inter-level dielectrics (ILD). Especially, defects like micro-scratch lead to severe circuit failure, and affect yield. CMP slurries can contain particles exceeding 1 μm size, which could cause micro-scratches on the wafer surface. The large particles in these slurries may be caused by particle agglomeration in slurry supply line. To reduce these defects, filtration has been recommended in oxide CMP. We have systematically studied the effects of filtration and the defect trend as a function of polished wafer count using various filters in inter-metal dielectric (IMD)-CMP process. The filter installation in CMP polisher could reduce defects after IMD-CMP process. Slurry filter plays an important role in determining consumable pad lifetime. The filter lifetime is dominated by the defects. Slurry filter lifetime is fixed by the degree of generating defects
Keywords :
VLSI; chemical mechanical polishing; dielectric thin films; failure analysis; filtration; integrated circuit interconnections; integrated circuit yield; 1 micron; chemical mechanical polishing; circuit failure; consumable pad lifetime; filtration; global planarization; inter-level dielectrics; inter-metal dielectric; micro-scratch formation; multi-level interconnections; particle agglomeration; polished wafer count; slurries; slurry filter; sub-micron technology; yield; Chemical engineering; Chemical processes; Chemical technology; Dielectrics; Filters; Filtration; Integrated circuit interconnections; Integrated circuit technology; Planarization; Slurries;
Conference_Titel :
Electrical Insulating Materials, 2001. (ISEIM 2001). Proceedings of 2001 International Symposium on
Conference_Location :
Himeji
Print_ISBN :
4-88686-053-2
DOI :
10.1109/ISEIM.2001.973571