Reconfigurable architecture for FIR filter with low power consumption

Low power reconfigurable architectural approach for finite impulse response(FIR) filter is proposed. This is suited for fixed filter order. To obtain reconfigurability in low power fir filter architecture variable input word length, different coefficient word length, reduced signal representation is used. In existing methods, low power is achieved by minimizing number of adders and multipliers. In the proposed method by considering the filter coefficient and inputs, filter dynamically changes the filter order to achieve dynamic power savings with minor degradation in performance. When the multiplication of input data and filter coefficient is so small the multiplication operation is cancelled and the multiplier is turned off to reduce the power consumption.