• DocumentCode
    2054794
  • Title

    Generation technique of 500 MHz ultra-high speed algorithmic pattern

  • Author

    Imada, Hideaki ; Fujisaki, Kenichi ; Ohsawa, Toshimi ; Tsuto, Masaru

  • Author_Institution
    Advantest Corp., Tokyo, Japan
  • fYear
    1996
  • fDate
    20-25 Oct 1996
  • Firstpage
    677
  • Lastpage
    684
  • Abstract
    This paper describes the pattern generation for testing ultra-high speed memory devices. 500 MHz algorithmic pattern can be generated by parallel operation with 4 pattern generators and arithmetic synthesis supported by a new pattern compiler
  • Keywords
    CMOS memory circuits; automatic testing; built-in self test; fault diagnosis; integrated circuit testing; very high speed integrated circuits; 500 MHz; XC register; arithmetic synthesis; flow chart; jump instructions; large scale CMOS gate array; multiple-function arithmetic unit; parallel operation; pattern compiler; pattern generation; pattern sequence control; ultrahigh speed algorithmic pattern; ultrahigh speed memory device testing; Arithmetic; CMOS logic circuits; Counting circuits; Electronic equipment testing; Flowcharts; Logic devices; Logic gates; System testing; Test pattern generators; Time frequency analysis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1996. Proceedings., International
  • Conference_Location
    Washington, DC
  • ISSN
    1089-3539
  • Print_ISBN
    0-7803-3541-4
  • Type

    conf

  • DOI
    10.1109/TEST.1996.557125
  • Filename
    557125
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2054794