Title :
Analysis and detection of timing failures in an experimental Test Chip
Author :
Franco, Piero ; Ma, Siyad ; Chang, Jonathan ; Chu, Yi-Chin ; Wattal, Sanjay ; McCluskey, E.J. ; Stokes, Robert L. ; Farwell, William D.
Author_Institution :
Center for Reliable Comput., Stanford Univ., CA, USA
Abstract :
A 25 k gate Test Chip was designed and manufactured to evaluate different test methods for scan-designed circuits. The design of the chip, the experiment, and preliminary experimental results were presented at ITC´95. This paper presents results for different clock speeds and clocking modes (at-speed and delay), and uses this data to characterize the behavior of the defective parts. It was found that timing-related defects are common, and the escape rate for different test techniques on these parts is discussed
Keywords :
CMOS logic circuits; automatic testing; boundary scan testing; clocks; combinational circuits; fault diagnosis; integrated circuit testing; logic testing; timing; CMOS gate array; at-speed; clock speed; clocking modes; combinational circuits; control logic; datapath logic; defective parts; delay; deterministic ATPG vectors; escape rate; full-scan circuits; response analysis; scan-designed circuits; signature analysis; stability checking; test chip; timing failures; timing-related defects; CMOS logic circuits; Circuit stability; Circuit testing; Clocks; Failure analysis; Logic arrays; Logic testing; Manufacturing; Propagation delay; Timing;
Conference_Titel :
Test Conference, 1996. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-3541-4
DOI :
10.1109/TEST.1996.557127
