Design optimization of analog integrated circuits by using artificial neural networks

Author

Jafari, A. ; Sadri, S. ; Zekri, M.

Author_Institution

Dept. of Electr. Eng., Islamic Azad Univ., Isfahan, Iran

fYear

2010

fDate

7-10 Dec. 2010

Firstpage

385

Lastpage

388

Abstract

This paper presents a computer-aided design (CAD) tool for automated sizing and optimization of analog integrated circuits (ICs). This tool uses artificial neural networks (ANNs) in order to deduce the device sizes that optimize the performance objectives while satisfying the constraint specifications. Neural networks can learn and generalize from data allowing model development even when component formulas are unavailable. The training data are obtained by various simulations in the HSPICE design environment with TSMC 0.18 μm CMOS process parameters. To evaluate the tool, one practical example is presented in 0.18 μm CMOS technology. The simulation results verify effectiveness of the proposed method for analog circuits sizing.

Keywords

CMOS integrated circuits; analogue integrated circuits; circuit CAD; circuit optimisation; neural nets; CMOS technology; HSPICE design; analog circuits sizing; analog integrated circuits; artificial neural networks; computer aided design; design optimization; model development; size 0.18 mum; Artificial neural networks; CMOS integrated circuits; Data models; Design automation; Integrated circuit modeling; Mathematical model; Optimization; analog integrated circuits; computer-aided design; multilayer perceptron; neural networks; optimization;

fLanguage

English

Publisher

ieee

Conference_Titel

Soft Computing and Pattern Recognition (SoCPaR), 2010 International Conference of

Conference_Location

Paris

Print_ISBN

978-1-4244-7897-2

Type

conf

DOI

10.1109/SOCPAR.2010.5686736

Filename

5686736