• DocumentCode
    2056267
  • Title

    An efficient encoding method for LDPC codes based on cyclic shift

  • Author

    Fujita, Hachiro ; Sakaniwa, Kohichi

  • Author_Institution
    Dept. of Commun. & Integrated Syst., Tokyo Inst. of Technol., Japan
  • fYear
    2004
  • fDate
    27 June-2 July 2004
  • Firstpage
    276
  • Abstract
    Low-density parity-check (LDPC) codes are one of the most promising next generation error correcting codes and many investigations shows that LDPC codes suitable for many hardware implementation. Although randomly constructed LDPC codes are usually encoded by using generator matrix, this method requires quadratic time complexity and is not easy to implement. This work presents the encoding of array-type LDPC codes and a special class of Sridhara-Fuja-Tanner (SFT) codes by division circuits as cyclic codes, which are very easy to implement.
  • Keywords
    cyclic codes; error correction codes; matrix algebra; parity check codes; SFT codes; Sridhara-Fuja-Tanner codes; array-type LDPC codes; cyclic codes; division circuit; error correcting code; low-density parity-check code; Circuits; Electronic mail; Encoding; Error correction codes; Galois fields; Hamming distance; Hardware; Parity check codes; Polynomials; Reed-Solomon codes;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Information Theory, 2004. ISIT 2004. Proceedings. International Symposium on
  • Print_ISBN
    0-7803-8280-3
  • Type

    conf

  • DOI
    10.1109/ISIT.2004.1365312
  • Filename
    1365312