Modeling multi-threaded architectures in PAMELA for real-time high performance applications

Presents a method to explore the design space of multi-threaded architectures using PAMELA (PerformAnce ModEling LAnguage). The domain of applications we consider is digital signal processing (DSP), where high performance is derived by exploiting both fine-grain and coarse-grain parallelism in the application. The modeling scheme takes an unified view of both fine-grain and coarse-grain parallelism in a given application to measure the performance of the architecture. The application-written using a high-level language-is compiled, and a trace generated for benchmark data in terms of the instruction set architecture of the processor. The generated trace is for a single uni-threaded, uni-processor system. This trace is pre-processed and re-targeted to generate multi-threaded architecture-specific PAMELA code. Using a material-oriented approach, the resulting PAMELA code is executed to evaluate various architecture options over the entire design space iteratively, subject to implementation constraints. We demonstrate the suitability and simplicity of the approach with an example