ASIC BIST synthesis: a VHDL approach

This paper describes the practical aspects of an automated design process and tool environment developed to rapidly and effectively include BIST into ASIC designs. An overview of the BIST architecture is given describing BIST capabilities for ASIC mission logic, embedded and external memory, devices, and an interconnect BIST capability used to assist module/PCB BIST. A high level synthesis approach is employed using the VHDL language in a way unique to its intended purpose. An automatic means for instantiating VHDL BIST structures into an ASIC design is described. Other automated phases of the development cycle are discussed including testability enhancement of the ASIC core and test stimulus generation for foundry, factory, and field test. Results are presented for 6 ASIC designs ranging in gate count from 56 k-164 k gates (complexity from controllers to data processors)