Title :
Production IDDQ testing with passive current compensation
Author :
Maston, Gregory A.
Author_Institution :
Div. of Application Specific Integrated Circuits, Motorola Inc., Chandler, AZ, USA
Abstract :
In an ideal world, all test vectors selected as IDDQ test vectors would have very low measurement current. In many circumstances, however, a complete set of tests cannot be defined when relying on zero-current considerations. IDDQ test vectors selected from existing test sets must be capable of compensating for passive currents. The identification of valid test vectors, and the magnitude of the passive current, can be predicted in the ASIC environment via macrocell-specific information. This paper presents one methodology to support this test generation using digital simulation, including the selection of multiple IDDQ test vectors
Keywords :
CMOS logic circuits; application specific integrated circuits; automatic test software; built-in self test; electric current measurement; fault diagnosis; integrated circuit testing; logic arrays; logic testing; production testing; ASIC; CMOS; dedicated current control pin; digital simulation; macrocell-specific information; multiple IDDQ test vectors; passive current compensation; power bus segmentation; production IDDQ testing; software requirements; test generation; valid test vectors identification; Application specific integrated circuits; Circuit faults; Circuit testing; Current measurement; Digital simulation; Fault detection; Integrated circuit measurements; Integrated circuit testing; Process design; Production;
Conference_Titel :
Test Conference, 1995. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2992-9
DOI :
10.1109/TEST.1995.529876
