Integrating scan into hierarchical synthesis methodologies

Author

Beausang, James ; Ellingham, Chris ; Robinson, Markus

Author_Institution

Synopsys Inc., Mountain View, CA, USA

fYear

1996

fDate

20-25 Oct 1996

Firstpage

751

Lastpage

756

Abstract

This paper presents new strategies for integrating scan DFT (design for test) techniques into hierarchical synthesis methodologies to meet the challenges of system-on-a-chip ICs (integrated circuits). It describes what can be done before, during and after synthesis to reduce design time, and presents results that show the effects of select approaches

Keywords

circuit CAD; design for testability; hardware description languages; hierarchical systems; high level synthesis; integrated circuit design; CAD; HDL; design for test; design management; hierarchical synthesis; hierarchical synthesis methodologies; system-on-a-chip IC; Circuit testing; Constraint optimization; Design for testability; Design methodology; Design optimization; Integrated circuit synthesis; Libraries; Logic testing; System testing; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1996. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-3541-4

Type

conf

DOI

10.1109/TEST.1996.557134

Filename

557134

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2057091