Title :
Integrating scan into hierarchical synthesis methodologies
Author :
Beausang, James ; Ellingham, Chris ; Robinson, Markus
Author_Institution :
Synopsys Inc., Mountain View, CA, USA
Abstract :
This paper presents new strategies for integrating scan DFT (design for test) techniques into hierarchical synthesis methodologies to meet the challenges of system-on-a-chip ICs (integrated circuits). It describes what can be done before, during and after synthesis to reduce design time, and presents results that show the effects of select approaches
Keywords :
circuit CAD; design for testability; hardware description languages; hierarchical systems; high level synthesis; integrated circuit design; CAD; HDL; design for test; design management; hierarchical synthesis; hierarchical synthesis methodologies; system-on-a-chip IC; Circuit testing; Constraint optimization; Design for testability; Design methodology; Design optimization; Integrated circuit synthesis; Libraries; Logic testing; System testing; Timing;
Conference_Titel :
Test Conference, 1996. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-3541-4
DOI :
10.1109/TEST.1996.557134
