DocumentCode
2057210
Title
A 50-MHz 10-ns submicron BiCMOS 2-way set associative cache tag memory
Author
Chiu, Edison H. ; An, Quang Dieu
Author_Institution
Texas Instrum. Inc., Dallas, TX, USA
fYear
1991
fDate
12-15 May 1991
Abstract
A highly-integrated 88-kb two-way set associative cache tag memory fabricated using 0.8-μm BiCMOS technology has been developed. The device integrates two 8 K×5 RAMs for tag and parity storage, one 8 K×1 least recently used (LRU) RAM, and the associated cache interface control logic. The die area is 4.9 mm×6.9 mm. Address to MATCH delay is 10 ns, and all three RAM cells can be reset in less than 8 ns. In addition, active power consumption is less than 750 mW at 5 V
Keywords
BIMOS integrated circuits; buffer storage; content-addressable storage; integrated memory circuits; random-access storage; 0.8 micron; 10 ns; 5 V; 50 MHz; 750 mW; 88 kbit; RAM; active power consumption; associative cache tag memory; cache interface control logic; parity storage; submicron BiCMOS; two-way set; BiCMOS integrated circuits; CMOS process; CMOS technology; Cache memory; Energy consumption; Impedance matching; Microprocessors; Random access memory; Read-write memory; Technical Activities Guide -TAG;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location
San Diego, CA
Print_ISBN
0-7803-0015-7
Type
conf
DOI
10.1109/CICC.1991.163987
Filename
163987
Link To Document