DocumentCode :
2057254
Title :
Quaternionic vs. conventional factorizations for fixed-point 4-channel general paraunitary filter bank
Author :
Parfieniuk, Marek ; Petrovsky, Alexander
Author_Institution :
Dept. of Real-Time Syst., Bialystok Tech. Univ., Poland
Volume :
2
fYear :
2005
fDate :
14-15 July 2005
Firstpage :
433
Abstract :
Both a review and a comparison of die known factorizations for 4-channel general paraunitary filter bank are made from the perspective of its fixed-point hardware implementation on FPGA. The sensitivity to coefficient quantization, as well as the design and computational complexity are analyzed. The main aim is to refer quaternionic building block to dyadic-based factorizations and lifting schemes.
Keywords :
channel bank filters; computational complexity; field programmable gate arrays; coefficient quantization; computational complexity; dyadic factorizations; field programmable gate array; fixed point hardware implementation; general paraunitary filter bank; quaternionic building block; quaternionic factorizations; Buildings; Computational complexity; Field programmable gate arrays; Filter bank; Hardware; Lattices; Matrix decomposition; Quantization; Quaternions; Signal processing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signals, Circuits and Systems, 2005. ISSCS 2005. International Symposium on
Print_ISBN :
0-7803-9029-6
Type :
conf
DOI :
10.1109/ISSCS.2005.1511270
Filename :
1511270
Link To Document :
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