Top down nano technologies in production of integrated circuits and surface modification of materials

As microelectronic devices continue to shrink and process requirements become ever more stringent, plasma modeling and simulation becomes increasingly more attractive as a tool for design, control and optimization of plasma reactors. Nowadays, plasma- etching processes are expected to produce patterns from the nanometer to the micrometer range. Charging effects in the etching of dielectrics due to ions accumulation in the shallow trenches or contact hole cause damage such as notching and earlier etching stop. In this article, a brief overview of the plasma etch process with emphasis on charging induced damage has been made. In addition, a level set method was applied to the 3D simulation of the etching profile of high aspect ratio trenches into silicon. Calculations were performed in the case of simplified model of Ar⁺/CF₄ non-equilibrium plasma etching of SiO₂. The time dependence of the profile charging as well as charging on profile during SiO₂ etching in plasma are presented. We shall also illustrate the properties of etching of organic low-k dielectrics.