Timing-driven test point insertion for full-scan and partial-scan BIST

We propose timing-driven test point insertion methods for a full-scan based BIST scheme and for a partial-scan based BIST scheme, where the global flip-flop cycles have been broken by the scan flip-flops. The objective is to minimize the performance as well as the area impact due to the insertion of test points while achieving a high fault coverage under the pseudo-random BIST scheme. The gradient-based method is used and extended to estimate the random-pattern testability improvement factors for the test point candidates of either full-scan based or partial-scan based BIST. We also propose a symbolic computation technique to compute testability for circuits under the partial-scan based BIST scheme. Experimental results show that the performance degradation of test point insertion could be unacceptably high if the cost function used for test point selection does not include the performance penalty. Using our timing-driven algorithm, zero performance degradation and a high fault coverage can always be achieved using a small number of test points