Scalable FIR filtering on transport triggered architecture processor

FIR filtering is an inevitable DSP operation in a wide variety of applications. In this paper, a processor based FIR filter, which is scalable in terms of multiply and accumulate units, is presented. The transport triggered architecture processor is accompanied with resources, which accelerate the FIR filtering. Depending on the number of resources, parallel code is configured to achieve high utilization of hardware. The main benefit of adapting the computing resources close to the computational load is efficient resource utilization and thereby savings in cost.