DocumentCode
2057783
Title
Test point insertion for an area efficient BIST
Author
Schotten, Claw ; Meyr, Heinrich
Author_Institution
Inst. for Int. Syst. in Signal Process., Aachen Univ. of Technol., Germany
fYear
1995
fDate
21-25 Oct 1995
Firstpage
515
Lastpage
523
Abstract
We present a new cost based method for the insertion of test points into sequential circuits. It is especially suited for the design of an area efficient BIST using pseudorandom patterns. Testability analysis is used to detect areas of poor testability and estimate the benefit of test points. The designer can trade this benefit against increased area. Experimental results show that small sets of test points are sufficient to reach a fault coverage greater than 99%
Keywords
automatic testing; built-in self test; design for testability; integrated circuit testing; logic testing; sequential circuits; area efficient BIST; cost based method; fault coverage; pseudorandom patterns; sequential circuits; test point insertion; testability analysis; Automatic testing; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Compaction; Costs; Logic testing; Sequential circuits; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1995. Proceedings., International
Conference_Location
Washington, DC
ISSN
1089-3539
Print_ISBN
0-7803-2992-9
Type
conf
DOI
10.1109/TEST.1995.529879
Filename
529879
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