DocumentCode :
2058086
Title :
Low Complexity DVB-S2 LDPC Decoder
Author :
Zhang, Botao ; Liu, Hengzhu ; Chen, Xucan ; Liu, Dongpei ; Yi, Xiaofei
Author_Institution :
Sch. of Comput. Sci., Nat. Univ. of Defense Technol., Changsha
fYear :
2009
fDate :
26-29 April 2009
Firstpage :
1
Lastpage :
5
Abstract :
The decoding complexity is the main issue in designing DVB-S2 Low Density Parity Check (LDPC) decoder. This paper proposes a low complexity decoder, which is based on a new row message passing Offset Min-Sum algorithm. The proposed algorithm can reduce the complexity of the decoder with no performance loss. The simplified node update units based on the proposed algorithm and the memory organization optimized across different code rates play the key role in reducing the complexity. The synthesized area of the decoder is 9.6 mm2 in Chartered 90 nm COMS technology. When the code rate is 9/10 and the work frequency is 320 MHz, the net throughput of the decoder is 998 Mbps.
Keywords :
digital video broadcasting; parity check codes; video coding; COMS technology; low complexity DVB-S2 LDPC decoder; low density parity check decoder; row message passing offset min-sum algorithm; Bit error rate; Code standards; Computer science; Digital video broadcasting; Iterative decoding; Message passing; Microprocessors; Parity check codes; Scheduling algorithm; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Vehicular Technology Conference, 2009. VTC Spring 2009. IEEE 69th
Conference_Location :
Barcelona
ISSN :
1550-2252
Print_ISBN :
978-1-4244-2517-4
Electronic_ISBN :
1550-2252
Type :
conf
DOI :
10.1109/VETECS.2009.5073653
Filename :
5073653
Link To Document :
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