DocumentCode
2058091
Title
IDDQ and voltage testable CMOS flip-flop configurations
Author
Sachdev, Manoj
Author_Institution
Philips Res. Lab., Eindhoven, Netherlands
fYear
1995
fDate
21-25 Oct 1995
Firstpage
534
Lastpage
543
Abstract
The controllability condition in sequential circuits is not enough for IDDQ detection of a class of bridging faults. Special DfT measures are needed to detect such bridging faults by IDDQ test technique. In this article, we propose two flip-flop configurations which are inherently IDDQ as well as voltage testable. Therefore, in these configurations, the controllability condition is sufficient for IDDQ testing of bridging faults and need for special DfT measures is no longer required. An additional inverter is needed to change popular master-slave flip-flop configurations into these configurations. The IDDQ test strategy and timing impact of the modification are also examined
Keywords
CMOS logic circuits; automatic testing; design for testability; flip-flops; integrated circuit testing; logic testing; sequential circuits; timing; CMOS; DfT measures; IDDQ testing; bridging faults; controllability condition; flip-flop configurations; master-slave flip-flop configurations; sequential circuits; timing; voltage testable circuits; Circuit faults; Circuit testing; Controllability; Electrical fault detection; Fault detection; Flip-flops; Inverters; Master-slave; Sequential circuits; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1995. Proceedings., International
Conference_Location
Washington, DC
ISSN
1089-3539
Print_ISBN
0-7803-2992-9
Type
conf
DOI
10.1109/TEST.1995.529881
Filename
529881
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