IDDQ and voltage testable CMOS flip-flop configurations

The controllability condition in sequential circuits is not enough for I_DDQ detection of a class of bridging faults. Special DfT measures are needed to detect such bridging faults by I_DDQ test technique. In this article, we propose two flip-flop configurations which are inherently I_DDQ as well as voltage testable. Therefore, in these configurations, the controllability condition is sufficient for I_DDQ testing of bridging faults and need for special DfT measures is no longer required. An additional inverter is needed to change popular master-slave flip-flop configurations into these configurations. The I_DDQ test strategy and timing impact of the modification are also examined