DocumentCode :
2058305
Title :
FPGA implementation of Alamouti MIMO log-likelihood ratio selection for receiver-antenna selection combining
Author :
Chow, Peiwang ; Chau, Yawgeng A. ; Ren, Guangliang
Author_Institution :
Dept. of Telecommun., Xidian Univ., Xi´´an, China
fYear :
2012
fDate :
19-21 April 2012
Firstpage :
116
Lastpage :
117
Abstract :
The Alamouti multiple-input multiple-output (MIMO) detector based on the log-likelihood ratio (LLR) selection statistic for receiver-antenna selection combining (SC) is implemented on an FPGA platform, where hardware simulation using Verilog HDL is illustrated, and the BPSK signaling is considered.
Keywords :
MIMO communication; diversity reception; field programmable gate arrays; hardware description languages; phase shift keying; receiving antennas; statistical analysis; Alamouti MIMO; BPSK signaling; FPGA; LLR selection statistic; Verilog HDL; log likelihood ratio; multiple input multiple output; receiver antenna; selection combining; Lead; Receivers; Transmitters; Alamouti space-time block code (STBC); FPGA; log-likelihood ratio (LLR); multiple-input multiple-output (MIMO); selection combining (SC);
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Wireless and Optical Communications Conference (WOCC), 2012 21st Annual
Conference_Location :
Kaohsiung
Print_ISBN :
978-1-4673-0940-0
Type :
conf
DOI :
10.1109/WOCC.2012.6198161
Filename :
6198161
Link To Document :
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