Title :
An edge-defined nano-lithography technique suitable for low thermal budget process and 3-D stackable devices
Author :
Nasrullah, Jawad ; Burr, James B. ; Tyler, G. Leonard
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., CA, USA
Abstract :
Edge-defined nano-meter scale lines patterned in silicon using 1μm optical lithography with standard materials and processing equipment are compatible with low thermal budget 3-D IC processes. A chemical vapor deposition (CVD) process is used to define spacers, around optically registered edges, that are combined with the photoresist mask to pattern underlying layers. Good control of CVD and dry etching enables patterning of features from 180 nm to 180 nm. Local critical dimension (CD) variations of up to ∼7 nm are observed, based on CD-SEM analysis. Spacer film roughness, oxide dry etch, and edge registration lithography contribute to CD variation and line-edge roughness.
Keywords :
chemical vapour deposition; elemental semiconductors; etching; interface roughness; masks; nanolithography; photolithography; photoresists; scanning electron microscopy; semiconductor devices; silicon; surface roughness; 180 to 18 nm; 3D stackable devices; 7 nm; CD variation; CVD; Si; chemical vapor deposition; critical dimension; dry etching; edge defined nanolithography; edge registration lithography; line edge roughness; low thermal budget process; optical lithography; optically registered edges; photoresist mask; spacer film roughness; underlying layers; Crystallization; Etching; Grain boundaries; Lithography; Nanoscale devices; Optical films; Silicon; Temperature; Thermal engineering; Three-dimensional integrated circuits;
Conference_Titel :
Nanotechnology, 2003. IEEE-NANO 2003. 2003 Third IEEE Conference on
Print_ISBN :
0-7803-7976-4
DOI :
10.1109/NANO.2003.1230956
