Back-annotation of timing information into a formal hardware model: a case study

In this paper we present a back-annotation of timing information into a formal hardware component. The formal model is represented using timed action system with which we are able to model temporal properties of a system in addition to functional properties. We give a low-level timed action system model for a protocol processor´s basic components. For these components we have corresponding synthesizable VHDL models. The timing information is obtained from the synthesized VHDL model, and the tenability of the timing is verified against the given time constraints. Time constraints are used to ensure that the timed action system model fulfills its timing obligations.