Title :
Buried Mask Revelation in Silicon Dioxide for Double Gate MOS Fabrication
Author :
Charavel, R. ; Raskin, J.P.
Author_Institution :
CERMIN, Univ. Catholique de Louvain, Louvain-la-Neuve
Abstract :
A new process for self-aligned double gate MOS fabrication is proposed. The milestone of this process in the revelation of a buried mask in the BOX of a SOI wafer and in a thermal oxide layer on top of active silicon film. The revelation of the buried mask makes use of the highly selective etching of implanted oxide in VHF. The etching mechanism of VHF etching of oxide is presented and the influence of the VHF etching parameters like temperature and etching time are discussed to prove the feasibility of this process step in order to integrate it in the whole process
Keywords :
MIS devices; buried layers; etching; masks; silicon compounds; silicon-on-insulator; SOI wafer BOX; SiO2; VHF etching parameters; VHF oxide etching mechanism; active silicon film; buried mask revelation; buried oxide; etching temperature; etching time; metal oxide semiconductor; selective implanted oxide etching; self aligned double gate MOS fabrication; silicon dioxide; silicon-on-insulator; thermal oxide layer; CMOS technology; Doping; Etching; Fabrication; FinFETs; Isolation technology; Parasitic capacitance; Semiconductor films; Silicon compounds; Silicon on insulator technology;
Conference_Titel :
Nano/Micro Engineered and Molecular Systems, 2006. NEMS '06. 1st IEEE International Conference on
Conference_Location :
Zhuhai
Print_ISBN :
1-4244-0139-9
Electronic_ISBN :
1-4244-0140-2
DOI :
10.1109/NEMS.2006.334668
