Real-time implementation of noise-immune gradient-based edge detection

This paper describes the implementation of a computational FPGA for edge detection, which particularly is immune to noise by a digital approximated Gaussian smoothing filter. Proposed systolic array architecture has been examined for convolution operation, which benefits the design with simplicity and regularity. Moreover, most of the presented processing structures are highly pipelined thus the goal of a real-time computing is substantially achieved with a frame rate up to 202 frames/sec. For the efficiency of hardware mapping to certain algorithm, the absolute difference mask (ADM) is adopted for its regularity and independent operations, as well as the valuable property of performing one-pixel-edge localization. A scalable FIFO design is also proposed, which makes the edge detector applicable for five different image sizes. The FPGA implementation on a versatile development platform results that our design improves the speed and hardware usage. This is attributed to the utilization of the proposed parallel and pipelined structure, so that a fast operation speed of 53MHz is obtained in this investigation, which is 83 times faster than software implementation.