GP based transistor sizing for optimal design of nanoscale CMOS inverter

This paper proposes a simple method to formulate the transistor sizing problem as a geometric program (GP) by using a modified I-V model which performs well up to 10 nm. The geometric program model for dynamic power delay product (PDP) expression has been formulated by using the modified I-V model for nanoscale CMOS inverter. The model has been solved efficiently, which generates a number of important practical consequences. This method computes the absolute limit of performance for given input frequency and load capacitance of a transistor and technology parameters. The accuracy of performance prediction in the transistor-sizing (through geometric programming) problem is verified due to its closeness to SPICE simulation (250 nm) results. Further the approach has been extended to predict the transistor sizing for nanoscale (up to 50 nm) CMOS inverter and the simulation results of the proposed model are compared with the Berkeley Predictive Technology Model (BPTM) to establish the usefulness of the approach.