A wide-range power-efficient CMOS phase-locked loop with a differential range-programmable VCO

CMOS phase-locked loop (PLL) equipped with a high-sensitivity phase/frequency detector (PFD) and a differential range-programmable low-noise voltage-controlled oscillator (VCO) is described. The PFD possesses a wide linear-range in its phase-detector characteristics and a high frequency-sensitivity. A full-switching low-noise differential delay cell is designed and employed to implement the differential range-programmable ring oscillator. Dual-delay path scheme is employed and leads to higher and wider output frequency range. A wide output-frequency range, from 85MHz to 136GHz, is achieved from the VCO in a power-efficient manner. The differential range-programmable ring oscillator shows substantial improvement in its output jitters, according to our jitter simulation in the presence of supply noise.