DocumentCode :
2058727
Title :
Application of boundary scan in a fault tolerant computer system
Author :
Boutin, Matthew ; Dziel, Peter
Author_Institution :
DFT Grou, Stratus Comput. Inc., Marlboro, MA, USA
fYear :
1996
fDate :
20-25 Oct 1996
Firstpage :
809
Lastpage :
817
Abstract :
With the successful implementation of boundary scan as a tool for board test, there is a natural evolution towards using this powerful technique for system level test. Testing of back panel assemblies has traditionally been left to operating system or deterministic diagnostic tests. The fault detection capabilities of these tests is usually adequate, but an opportunity for improvement exists in the isolation of faults to a specific pin or device. Use of “board to board” boundary scan addresses this problem as well as several others. This paper describes the implementation of boundary scan in a Stratus Computer system both at the board and system level and discusses general hardware and software requirements. It outlines the cost savings of converting from the traditional approach
Keywords :
DP industry; boundary scan testing; computer testing; economics; fault tolerant computing; printed circuit testing; Stratus cmputer system; back panel assemblies; boundary scan; boundary scan addresses; deterministic diagnostic tests; fault detection; fault tolerant computer system; hardware requirements; software requirements; system level test; Application software; Assembly systems; Automatic test pattern generation; Circuit testing; Costs; Fault detection; Fault tolerant systems; Hardware; Software testing; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 1996. Proceedings., International
Conference_Location :
Washington, DC
ISSN :
1089-3539
Print_ISBN :
0-7803-3541-4
Type :
conf
DOI :
10.1109/TEST.1996.557141
Filename :
557141
Link To Document :
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