A linear CMOS voltage-to-current converter

An improved CMOS voltage-to-current converter is presented. PMOS transistors are employed in the resistor-replacement and voltage-level shifting of the proposed converter to avoid the body effect. To accurately annihilate the nonlinear voltage terms, a better modeling of the drain-to-source current of the MOS transistor operating in the linear region is essential and is adopted. Specifically the substrate-bias effect of the MOS transistor is treated more thoroughly in our design. Consequently, the nonlinearity of the large-signal transresistance of the converter, caused mainly by the body effect of a NMOS transistor in a previously published converter, is greatly minimized. The voltage-to-current converter is designed and fabricated in a 0.35 μm CMOS technology. The fabricated circuit occupies an area of 430 μm × 260 μm (≈12mm^-2) and dissipates less than 2.2 mW from a 3.3 V supply. The measured and simulated data are in good agreement. For a 1 V_P-P input voltage, the total harmonic distortion (THD) of the output current is less than 1.5%.