High-level test generation using symbolic scheduling

Author

Hansen, Mark C. ; Hayes, John P.

Author_Institution

Design Autom. Oper., Delco Electron. Corp., Kokomo, IN, USA

fYear

1995

fDate

21-25 Oct 1995

Firstpage

586

Lastpage

595

Abstract

A high-level test generation algorithm SWIFT is proposed which incorporates a symbolic scheduling procedure, derived from high-level synthesis applications, to resolve decision conflicts during test generation. SWIFT uses the induced fault model to generate functional tests that guarantee detection of low-level structural faults. When applied to functional models of representative 74 X-series, ISCAS-85 and ISCAS-89 circuits. SWIFT produces test sequences that cover all gate-level stuck-at-faults. Surprisingly, although they are derived from a high-level functional description of the circuit under test, most of these test sequences are of provably minimal or near-minimal size

Keywords

automatic testing; fault location; integrated circuit testing; logic testing; scheduling; sequential circuits; timing; 74 X-series; ATPG; IC testing; ISCAS-85 circuits; ISCAS-89 circuits; SWIFT; decision conflicts; functional tests; gate-level stuck-at-faults; high-level functional description; high-level test generation; low-level structural faults; symbolic scheduling; test generation; test sequences; Automatic test pattern generation; Circuit faults; Circuit testing; Clocks; Electronic equipment testing; Integrated circuit modeling; Integrated circuit testing; Logic testing; Sequential analysis; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1995. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-2992-9

Type

conf

DOI

10.1109/TEST.1995.529887

Filename

529887