Title :
Hierarchical functional fault simulation for high-level synthesis
Author :
Kassab, M. ; Rajski, J. ; Tyszer, J.
Author_Institution :
MACS Lab., McGill Univ., Montreal, Que., Canada
Abstract :
A novel highly efficient fault simulation technique targeted for circuits produced through high-level synthesis is presented. The technique combines hierarchical and functional fault simulation of commonly used building blocks that have regular structures. Comparison with gate-level simulation demonstrates the advantage of using this technique for this class of circuits
Keywords :
built-in self test; circuit analysis computing; digital simulation; high level synthesis; minimisation of switching nets; benchmark circuits; hierarchical functional fault simulation; high-level synthesis; logic simulation; regular structures; Arithmetic; Automatic testing; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Compaction; Computational modeling; High level synthesis; Performance evaluation;
Conference_Titel :
Test Conference, 1995. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2992-9
DOI :
10.1109/TEST.1995.529888
