Using statistical models with duplication and compare for reduced cost FPGA reliability

Although highly reliable for fault mitigation, triple modular redundancy (TMR) in FPGAs comes with the price of increasing the circuit area (3-5x), decreasing the circuit clock rate (20+%), and increasing circuit power (3-5x). Techniques may exist that trade off some of the reliability of TMR for reduced costs in terms of area, timing, and power. This paper proposes one such technique which uses duplicate with compare (DWC) with the addition of a smart detector to predict which of the duplicated circuits is in error to choose the fault free circuit as output. The smart detector proposed in this paper is a simple statistical model with low-resource costs. The model and testing methodology employed is discussed as well as results from fault injection testing, which indicate that the proposed statistical smart detector exhibits 87% to 93% prediction accuracy.