A robust design for fully-silicided electrostatic discharge protection devices in sub-100 nm CMOS circuit era

In this paper we present a novel experimental methodology in studying a robust fully-silicided ESD protection device. The results demonstrate that the proposed floating body design is amenable to implement in sub-100 nm CMOS circuit. The design exhibits an excellent efficiency on both protection and chip area. This original technique is attractive to advanced CMOS circuit design; in particular for the consideration of ultra-thin gate-oxide reliability.