Title :
A robust design for fully-silicided electrostatic discharge protection devices in sub-100 nm CMOS circuit era
Author :
Lee, Jam-Wem ; Li, Yiming
Author_Institution :
Dept. of Nano Device Technol., Nat. Nano Device Lab., Hsinchu, Taiwan
Abstract :
In this paper we present a novel experimental methodology in studying a robust fully-silicided ESD protection device. The results demonstrate that the proposed floating body design is amenable to implement in sub-100 nm CMOS circuit. The design exhibits an excellent efficiency on both protection and chip area. This original technique is attractive to advanced CMOS circuit design; in particular for the consideration of ultra-thin gate-oxide reliability.
Keywords :
CMOS integrated circuits; electrostatic devices; electrostatic discharge; nanotechnology; semiconductor device models; 100 nm; CMOS circuit era; ESD protection device; chip area; floating body design; robust design; silicided electrostatic discharge protection devices; ultra thin gate oxide reliability; Biological system modeling; CMOS technology; Circuit synthesis; Electrostatic discharge; Laboratories; Nanoscale devices; Protection; Robustness; Very large scale integration; Voltage;
Conference_Titel :
Nanotechnology, 2003. IEEE-NANO 2003. 2003 Third IEEE Conference on
Print_ISBN :
0-7803-7976-4
DOI :
10.1109/NANO.2003.1230993
