An efficient fault-tolerance technique for the Keyed-Hash Message Authentication Code

The growing demand for secure communications has lead to the utilization of cryptographic mechanisms on-board spacecrafts. However, that it not a trivial task due to sensitivity of cryptographic primitives to bit-flips, which are commonly caused by the radiation found in space. On-board processing has mitigated single event upsets (SEUs) by employing the traditional triple modular redundancy (TMR), but that technique incurs into huge area and energy penalties. This paper introduces an efficient approach to achieve fault tolerance in data origin authentication mechanisms based on the Keyed-Hash Message Authentication Code (HMAC). The proposed scheme achieves very high resistance against SEUs while reducing implementation area requirements and energy consumption compared to TMR. Results obtained through FPGA implementation show that HMAC-SHA512 utilizes 53% less area and consumes 25% less energy compared to the traditional TMR technique. Furthermore, the memory and registers of this hardware module are respectively 386 and 1140 times more resistant against SEUs than TMR. These results are crucial for substituting TMR with more efficient strategies therefore contributing to the achievement of higher levels of security in space systems.