Title :
Yield learning via functional test data
Author :
Kwon, Young-Jun ; Walker, D.M.H.
Author_Institution :
Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
Abstract :
This paper presents a methodology to estimate the defect Pareto in an IC process through the use of production functional test data. This Pareto can then be used for yield improvement activities. We demonstrate the concept on several benchmark circuits. We show how limited IDDQ current testing can significantly improve the Pareto accuracy
Keywords :
Monte Carlo methods; VLSI; automatic test software; circuit analysis computing; circuit optimisation; electric current measurement; fault diagnosis; integrated circuit testing; integrated circuit yield; probability; production testing; ATPG; IC process; Monte Carlo simulator; VLASIC simulator; VLSI manufacture; benchmark circuits; defect Pareto; fault simulation; limited IDDQ current testing; local defects; production functional test data; yield improvement; yield learning; yield ramp; Circuit faults; Circuit simulation; Circuit testing; Computer science; Condition monitoring; Costs; Optical losses; Performance evaluation; Predictive models; Production;
Conference_Titel :
Test Conference, 1995. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2992-9
DOI :
10.1109/TEST.1995.529891
