Failure analysis for full-scan circuits

Author

De, Kaushik ; Gunda, Arun

Author_Institution

LSI Logic Corp., Milpitas, CA, USA

fYear

1995

fDate

21-25 Oct 1995

Firstpage

636

Lastpage

645

Abstract

We present a complete system for failure analysis of full-scan circuits. A novel scheme has been proposed to handle multiple faults up to a certain extent by ranking the faults according to the likelihood of being present in the defective part. The user can interactively recompute the suspect fault list by changing some parameters. If the suspect fault list is large, we generate new test patterns to distinguish the faults in the suspect list. User can iterate over a defective part several times until the suspect fault list is reasonably small. Then each suspect site is probed using E-beam. This tool is integrated into design environment of LSI Logic Corporation and produced good results when applied on a few industry circuits

Keywords

automatic test software; automatic testing; boundary scan testing; design for testability; electron beam testing; fault diagnosis; fault location; integrated circuit testing; logic testing; SCAN-FA tool; algorithm; electron beam probed; failure analysis; fault diagnosis; fault localisation; fault merit scale; full-scan circuits; integrated into design environment; multiple faults; stuck-at fault model; suspect fault list; test pattern generation; Circuit faults; Circuit testing; Dictionaries; Failure analysis; Fault diagnosis; Information analysis; Large scale integration; Logic circuits; Sequential circuits; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1995. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-2992-9

Type

conf

DOI

10.1109/TEST.1995.529892

Filename

529892