DocumentCode
2059635
Title
An experimental chip to evaluate test techniques: chip and experiment design
Author
Franco, Piero ; Farwell, William D. ; Stokes, Robert L. ; McCluskey, E.J.
Author_Institution
Center for Reliable Comput., Stanford Univ., CA, USA
fYear
1995
fDate
21-25 Oct 1995
Firstpage
653
Lastpage
662
Abstract
An experiment has been designed to evaluate multiple testing techniques for combinational circuits. To perform the experiment, a 25 k gate CMOS Test Chip has been designed, manufactured (5491 devices),and evaluated with over 300 tests. The chip contains five types of CUTs derived from functions in production ASICs
Keywords
CMOS logic circuits; application specific integrated circuits; automatic testing; combinational circuits; fault diagnosis; integrated circuit testing; logic arrays; logic testing; ASIC; ATE; CMOS test chip; circuits-under-test; combinational circuits; control logic blocks; dedicated gate array chip; logic circuit testing; multiple testing techniques; Aircraft; Application specific integrated circuits; Automatic testing; Circuit testing; Integrated circuit testing; Logic testing; Manufacturing; Performance evaluation; Production; Test equipment;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1995. Proceedings., International
Conference_Location
Washington, DC
ISSN
1089-3539
Print_ISBN
0-7803-2992-9
Type
conf
DOI
10.1109/TEST.1995.529894
Filename
529894
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