An experimental chip to evaluate test techniques experiment results

Author

Ma, Siyad C. ; Franco, Piero ; McCluskey, Edward J.

Author_Institution

Center for Reliable Comput., Stanford Univ., CA, USA

fYear

1995

fDate

21-25 Oct 1995

Firstpage

663

Lastpage

672

Abstract

This paper describes the testing of a chip especially designed to facilitate the evaluation of various test techniques for combinational circuitry. The different test sets and test conditions are described. Several tables show the results of voltage tests applied, either at rated speed or 2/3 speed, to each defective CUT. Data for CrossCheck, Very-Low-Voltage, IDDQ and delay tests are also given

Keywords

CMOS logic circuits; automatic testing; built-in self test; combinational circuits; design for testability; fault diagnosis; integrated circuit testing; logic testing; ASIC; ATPG; CMOS test chip; CrossCheck tests; IDDQ tests; combinational circuitry; control logic blocks; defective CUT; delay tests; design verification tests; multiple test techniques evaluation; multipliers; on-chip pattern generation; stuck-at faults; very-low-voltage tests; voltage tests; wafer sort test procedure; Circuit analysis; Circuit faults; Circuit testing; Combinational circuits; Delay; Large scale integration; Logic testing; Manufacturing; Test pattern generators; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1995. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-2992-9

Type

conf

DOI

10.1109/TEST.1995.529895

Filename

529895