Title :
Test synthesis in the behavioral domain
Author :
Papachristou, Christos ; Carletta, Joan
Author_Institution :
Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
Abstract :
A method for test synthesis in the behavioral domain is described. The approach is based on the addition of test behavior, which is the behavior of the design in test mode. The normal-mode design behavior and test-mode test behavior are combined and synthesized together to produce a testable design with inserted BIST structures. Derivation of an appropriate test behavior uses analysis based on metrics that quantify the testability of signals embedded within behaviors. The synthesized circuit is tested using a behavioral test scheme which allows the test controller to be easily embedded within the system controller, and the entire datapath and controller to be easily tested together. Results show that when the testability insertion procedure is used to modify a behavior before synthesis, the resulting synthesized physical implementation is indeed more easily tested than an implementation synthesized directly from the original behavior
Keywords :
automatic testing; built-in self test; data flow graphs; design for testability; fault diagnosis; hardware description languages; high level synthesis; logic CAD; logic partitioning; logic testing; VHDL; behavioral domain; behavioral test scheme; data flow graph; datapaths partition; design for testability; high fault coverage; high level synthesis; inserted BIST structures; normal-mode design behavior; test synthesis; test-mode test behavior; testability insertion procedure; testable design; Built-in self-test; Circuit synthesis; Circuit testing; Control system synthesis; Design for testability; High level synthesis; Logic testing; Semiconductor device testing; Signal synthesis; System testing;
Conference_Titel :
Test Conference, 1995. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2992-9
DOI :
10.1109/TEST.1995.529899
