Buck converter for low power applications

Buck converter for low power applications is designed and investigated on standard 0.35-mum CMOS process. The blocks of the system, including bandgap reference, ramp generator, error amplifier, comparator, buffer and power buck stage, are optimized using CADENCE design tools. The energy losses in the controlling stages are minimized in order to improve the overall converter efficiency eta. A relatively high switching frequency of about 147 MHz is used in order to decrease the size of the filtering components. Power efficiency of about 70% is achieved for voltage conversion from 3.6 V down to 1.2 V. The converter systems shows stable performance over temperature, input voltage, and output load variations.