DocumentCode
2059908
Title
Test synthesis: from wishful thinking to reality
Author
Ruparel, Kamalesh N.
Author_Institution
Apple Comput. Inc., Cupertino, CA, USA
fYear
1995
fDate
21-25 Oct 1995
Firstpage
738
Abstract
A few years ago, most people understood “test synthesis” to be a two-step process: first, analysis of the functionality of a design to exploit its inbuilt structural testability and second, to modify functionality for enhanced structural testability. Well, that was truly wishful thinking. The reality today, however, is that test synthesis now means adding test logic purely for the purposes of structural testability. Furthermore, as we get closer to the nuts and bolts of the process, it is interesting to note how the synthesis of test logic in a design becomes mostly a challenge to satisfy the target software tools (ATPG) and ATE requirements instead of addressing the enhancement of fault coverage
Keywords
automatic test equipment; automatic testing; fault diagnosis; integrated circuit testing; logic testing; software tools; ATE requirements; ATPG; fault coverage; structural testability; target software tools; test logic; test synthesis; Application specific integrated circuits; Automatic test pattern generation; Clocks; Design for testability; Fasteners; Logic design; Logic testing; Read-write memory; Software testing; Software tools;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1995. Proceedings., International
Conference_Location
Washington, DC
ISSN
1089-3539
Print_ISBN
0-7803-2992-9
Type
conf
DOI
10.1109/TEST.1995.529904
Filename
529904
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