Nonvolatile quantum dot memory (NVQDM) in floating gate configuration: device and circuit modeling

Author

Hasaneen, El-Sayed ; Rodriguez, A. ; Yarlagadda, B. ; Jain, F. ; Heller, E. ; Huang, W. ; Lee, J. ; Papadimitrakopoulos, F.

Author_Institution

Dept. of Electr. & Comput. Eng., Connecticut Univ., Storrs, CT, USA

Volume

2

fYear

2003

fDate

12-14 Aug. 2003

Firstpage

741

Abstract

In this paper, we describe the physical and circuit models of a nonvolatile memory cell comprising of CdSe nanocrystals in a floating gate configuration. The floating gate voltage is computed from the ratio of capacitances between the floating gate and control gate. Threshold voltage for the 0.07 μm channel length MOSFET is calculated using various device parameters including the effect of charge on nanocrystal quantum dots. Current voltage characteristics are obtained using BSIM3v3. The gate current is modeled based on direct tunneling between the channel and nanocrystals. Results for a 70 nm channel length device are presented.

Keywords

CMOS memory circuits; II-VI semiconductors; MOSFET; cadmium compounds; capacitance; nanostructured materials; self-assembly; semiconductor quantum dots; tunnelling; 0.07 micron; 70 nm; CdSe; CdSe nanocrystals; capacitances; channel length MOSFET; channel length device; circuit modeling; control gate; current voltage characteristics; device modeling; direct tunneling; floating gate configuration; floating gate voltage; gate current; nanocrystal quantum dots; nonvolatile memory cell; nonvolatile quantum dot memory; Circuits; MOSFETs; Nanocrystals; Nonvolatile memory; Quantum capacitance; Quantum dots; Threshold voltage; Tunneling; US Department of Transportation; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Nanotechnology, 2003. IEEE-NANO 2003. 2003 Third IEEE Conference on

Print_ISBN

0-7803-7976-4

Type

conf

DOI

10.1109/NANO.2003.1231019

Filename

1231019