• DocumentCode
    2060242
  • Title

    Improved boundary scan design

  • Author

    Whetsel, Lee

  • Author_Institution
    Texas Instrum. Inc., USA
  • fYear
    1995
  • fDate
    21-25 Oct 1995
  • Firstpage
    851
  • Lastpage
    860
  • Abstract
    This paper describes work regarding improvements in boundary scan cell design. The results of this work provide an innovative way to implement boundary scan cells (BSCs) on IC input, output, and input/output (I/O) pins. The new cell designs provide; (1) reduced cell size, (2) reduced signalling delay, (3) support for IDDQ testing, (4) protection of output buffers in the presence of shorts, and (5) a method of safely testing newly assembled boards
  • Keywords
    IEEE standards; automatic testing; boundary scan testing; design for testability; fault diagnosis; integrated circuit testing; logic testing; I/O pins; IDDQ testing support; IC input; IC output; IEEE 1149.1; boundary scan cell design; functional core logic; output buffers protection; reduced cell size; reduced signalling delay; shared resource boundary scan; shorts; Assembly; Circuit testing; Clamps; Delay; Instruments; Integrated circuit testing; Pins; Protection; Signal design; Standards Working Groups;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1995. Proceedings., International
  • Conference_Location
    Washington, DC
  • ISSN
    1089-3539
  • Print_ISBN
    0-7803-2992-9
  • Type

    conf

  • DOI
    10.1109/TEST.1995.529917
  • Filename
    529917
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2060242