Title :
Challenging the “high performance-high cost” paradigm in test
Author :
Schoettmer, Ulrich ; Minami, Toshiyuki
Author_Institution :
Hewlett-Packard GmbH, Boblingen, Germany
Abstract :
A breakthrough in cutting investment cost of high performance ATE has been achieved through “per pin vector processing”. This paper outlines this new test system architecture and its deployment for an advanced processor application
Keywords :
automatic test equipment; automatic test software; boundary scan testing; computer testing; cost-benefit analysis; fault diagnosis; integrated circuit testing; logic testing; vector processor systems; very high speed integrated circuits; ATPG; VLSI test; advanced processor application; compression per pin methodology; embedded cache application; gallop pattern; high cost; high performance ATE; high speed CMOS; investment cost; logic testing; memory testing; per pin vector processing; program flow; random access scan; test system architecture; vector memory addressing; Circuit testing; Cost function; DC generators; Design engineering; Electronic equipment testing; Integrated circuit testing; System testing; System-on-a-chip; Test pattern generators; Very large scale integration;
Conference_Titel :
Test Conference, 1995. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2992-9
DOI :
10.1109/TEST.1995.529919
