Title :
Intel386 EX embedded processor IDDQ testing
Author :
Ahuja, Hitesh ; Arriens, Dean ; Schneller, B. ; Verma, Vandana ; Whitman, Wendy
Author_Institution :
Semicond. Products Group, Intel Corp., Chandler, AZ, USA
Abstract :
IDDQ testing, along with stuck-at fault, AC timing, and DC testing is increasingly considered a necessity for good product quality. This paper presents an IDDQ vector selection methodology, along with vector implementation in the production test program. IDDQ fault seeding results show that by stuck-at fault modeling, we can detect single stuck-at nodes that were not detected before. A comparative evaluation of conventional testing methods and IDDQ testing is presented. Experimental test results are presented that ascertain the effectiveness of IDDQ particularly how it overlaps with stuck-at fault coverage. A practical method that estimates the test coverage overlap is applied to reduce the stuck-at improvement effort and obtain “credit” towards the Intel386 EX processor quality requirements for production. A follow-on experiment for obtaining more data is proposed and data are being collected
Keywords :
CMOS digital integrated circuits; automatic testing; computer testing; fault location; integrated circuit testing; production testing; real-time systems; CMOS circuits; IDDQ testing; Intel386 EX embedded processor; fault seeding; product quality; production test program; single stuck-at nodes; test coverage overlap; vector selection methodology; Circuit faults; Circuit testing; Clocks; Fault detection; Leak detection; Logic; Production; Semiconductor device testing; Switches; Timing;
Conference_Titel :
Test Conference, 1995. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2992-9
DOI :
10.1109/TEST.1995.529923
