Bandwidth Improvement of CMOS-APD With Carrier-Acceleration Technique

We present a silicon avalanche photodetector (APD) based on multiple P⁺/N-well junctions fabricated in standard complementary metal-oxide-semiconductor (CMOS) technology. In order to overcome the photodetection-bandwidth limitation of the CMOS-APD based on P⁺/N-well junction, carrier-acceleration technique is proposed. With this technique, the photogenerated carriers in the charge-neutral N-well region are accelerated by the extrinsic electric field. To induce the extrinsic electric field inside N-well, the CMOS-APD is designed with multiple junctions to reduce the distance between two different N-well biasing contacts. Its performance is simulated and measured with different bias voltages applied to N-well, and it is demonstrated that the CMOS-APD with the carrier-acceleration technique provides higher photodetection bandwidth.