Title :
3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS
Author :
Upadhyaya, Parag ; Savoj, Jafar ; Fu-Tai An ; Bekele, Ade ; Jose, Anup ; Xu, Bruce ; Wu, Daniel ; Furker, Didem ; Aslanzadeh, Hesam ; Hedayati, Hiva ; Im, Jay ; Siok-Wei Lim ; Chen, Stanley ; Toan Pham ; Frans, Yohan ; Ken Chang
Author_Institution :
Xilinx, San Jose, CA, USA
Abstract :
The introduction of high-speed backplane transceivers inside FPGAs has addressed critical issues such as the ease in scalability of performance, high availability, flexible architectures, the use of standards, and rapid time to market. These have been crucial to address the ever-increasing demand for bandwidth in communication and storage systems [1-3], requiring novel techniques in receiver (RX) and clocking circuits.
Keywords :
CMOS logic circuits; field programmable gate arrays; transceivers; CMOS; FPGA; bit rate 0.5 Gbit/s to 32.75 Gbit/s; clocking circuits; communication systems; current 3.3 A; flexible architectures; flexible-reach wireline transceiver; high-speed backplane transceivers; performance scalability; size 20 nm; storage systems; time-to-market; Bandwidth; CMOS integrated circuits; Clocks; Decision feedback equalizers; Phase locked loops; Receivers; Transceivers;
Conference_Titel :
Solid- State Circuits Conference - (ISSCC), 2015 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4799-6223-5
DOI :
10.1109/ISSCC.2015.7062923
