Generation of test cases for hardware design verification of a super-scalar Fetch Processor

Author

Pomeranz, Irith ; Saxena, Nirmal R. ; Reeve, Richard ; Kulkami, Paritosh ; Li, Yan A.

Author_Institution

Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA

fYear

1996

fDate

20-25 Oct 1996

Firstpage

904

Lastpage

913

Abstract

We describe a method to generate test cases (or test programs) for hardware design verification. The proposed method uses non-functional errors defined over a software model of the specification to guide the generation of test programs. Application of the proposed method to the Hal. super-scalar Fetch Processor is also described. For this design, we present experimental results to demonstrate the effectiveness of the method in achieving a high design error coverage with relatively short test programs

Keywords

automatic test software; computer testing; design for testability; integrated circuit testing; software engineering; effectiveness; error coverage; hardware design verification; non-functional errors; short test programs; software model; super-scalar Fetch Processor; Application software; Boolean functions; Computer aided software engineering; Computer errors; Data structures; Formal verification; Hardware; Logic; Microprocessors; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1996. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-3541-4

Type

conf

DOI

10.1109/TEST.1996.557152

Filename

557152