7.1 A low-power 64Gb MLC NAND-flash memory in 15nm CMOS technology

Author

Sako, Mario ; Watanabe, Yoshihisa ; Nakajima, Takao ; Sato, Jumpei ; Muraoka, Kazuyoshi ; Fujiu, Masaki ; Kouno, Fumihiro ; Nakagawa, Michio ; Masuda, Masami ; Kato, Koji ; Terada, Yuri ; Shimizu, Yuki ; Honma, Mitsuaki ; Imamoto, Akihiro ; Araya, Tomoko

Author_Institution

Toshiba Semicond. & Storage Products, Yokohama, Japan

fYear

2015

fDate

22-26 Feb. 2015

Firstpage

1

Lastpage

3

Abstract

The demand for high-throughput NAND Flash memory systems for mobile applications such as smart phones, tablets, and laptop PCs with solid-state drives (SSDs) has been growing recently. To obtain higher throughput, systems employ multiple NAND Flash memories operating simultaneously in parallel. The available power for a mobile device is severely restricted and the peak total operating current may be high enough to cause large supply-voltage drop or even an unexpected system shutdown. Therefore it is important for NAND Flash memories to reduce operating power and peak operating current.

Keywords

CMOS logic circuits; CMOS memory circuits; NAND circuits; flash memories; low-power electronics; smart phones; CMOS technology; SSD; high-throughput NAND flash memory systems; laptop PC; low-power MLC NAND-flash memory; mobile application; mobile device; multiple-NAND flash memories; operating power reduction; peak total operating current; size 15 nm; smart phones; solid-state drives; supply-voltage drop; tablets; CMOS integrated circuits; Charge pumps; Computer architecture; Flash memories; Microprocessors; Sensors; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid- State Circuits Conference - (ISSCC), 2015 IEEE International

Conference_Location

San Francisco, CA

Print_ISBN

978-1-4799-6223-5

Type

conf

DOI

10.1109/ISSCC.2015.7062959

Filename

7062959