Title :
Clock-Aware Placement for FPGAs
Author :
Lamoureux, Julien ; Wilton, Steven J E
Author_Institution :
Univ. of British Columbia, Vancouver
Abstract :
The programmable clock networks in FPGAs have a significant impact on overall power, area, and delay. Not only does the clock network itself dissipate a significant amount of power, since it connects to every latch on the FPGA and toggles every cycle, but the design of the clock network also affects how efficiently the rest of the application can be implemented since it imposes constraints on the CAD tools which map the application onto the FPGA. To examine this tradeoff, this paper describes and compares new clock-aware placement techniques and then examines how the clock network architecture affects overall power, area, and delay. Our results show that the placement techniques used to make placement clock-aware have a significant influence on power and delay. On average, circuits placed using the most effective techniques dissipate 9.9% less energy and were 2.4% faster than circuits placed using the least effective techniques. Moreover, the results show that the clock network architecture is also important. On average, FPGAs with an efficient clock network were up to 12.5% more energy efficient and 7.2% faster than other FPGAs.
Keywords :
clocks; field programmable gate arrays; programmable logic devices; technology CAD (electronics); CAD tools; FPGA; clock-aware placement; programmable clock network architecture; Circuits; Clocks; Costs; Delay; Design automation; Energy efficiency; Field programmable gate arrays; Latches; System-level design; Technological innovation;
Conference_Titel :
Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on
Conference_Location :
Amsterdam
Print_ISBN :
978-1-4244-1060-6
Electronic_ISBN :
978-1-4244-1060-6
DOI :
10.1109/FPL.2007.4380636